Current state of the art backplanes for AMOLED displays use a pixel driver circuit for each OLED, each pixel driver circuit driving a predetermined current through the corresponding OLED. Multiple pixel driver circuit schematics are being implemented, which all comprise a drive transistor (such as M1 in FIG. 1) driving the predetermined current through the OLED.
In an analog driving method an amplitude modulation approach is used, wherein each OLED emits light during a full frame period with an intensity corresponding to the required gray level. The current through the OLED is determined in accordance with an analog data voltage on the floating gate of the drive transistor M1. As this transistor M1 preferably operates in saturation for accurate current control, the current through the OLED (and thus the OLED luminance) varies with the square of the M1 gate voltage. This introduces non-linearity in the display response, limits accuracy and makes the display sensitive to noise. An overall display architecture as schematically shown in FIG. 2 is currently used for analog driven displays. At one edge of the display, a select line driver integrated circuit is provided. The select lines are digitally driven, for instance by a running one, cycling at a rate corresponding to the frame rate. At another edge of the display, data line driver circuitry is provided for driving the data lines. The data lines are driven by an analog voltage, keeping the pixels at a constant luminance during an entire image frame.
In a digital driving method a Pulse Width Modulation approach can be used, wherein each OLED emits light during a portion of a frame period, at a single luminance. In this approach the portion of the frame period during which an OLED emits light has a duration corresponding to the required gray level. A pulse current having a duty ratio in accordance with the data voltage is supplied to each OLED. In such known approach, a frame is divided into n sub-frames, wherein n is the number of bits used for digitally representing the image data. These n sub-frames may have a different duration, there being a ratio 1:2:4:8: . . . :2n−1 between the different sub-frame durations. In each sub-frame a pixel (OLED) is either ON or OFF. In this way 2n different gray levels can be created. A display architecture is used wherein select lines (for instance rows) are digitally driven by dedicated timing control circuitry and wherein data lines (for instance columns) are driven by a digital voltage, as schematically illustrated in FIG. 3.
US 2013/0141469 discloses a device for driving an AMOLED display comprising OLEDs arranged in rows and columns and a pixel circuit for driving each OLED, a scan line for selecting the pixel circuits of each row and a data line for controlling the pixel circuits of each column. Each OLED is controlled by scan signal (through the scan line) and signal generation (through the data line) using current pulses during a sub-frame with a duration depending of the bit position. OLEDs are driven the longest (longest sub-frame) for the data corresponding to the most significant bit, and the shortest (shortest sub-frame) for the least significant bit. This method requires a high power consumption and the utilization of the pixel illumination is discontinuous and suboptimal, and the implementation of colour depth above six bit is difficult.
FIG. 4 shows a comparison between a typical analog pixel driving method (dashed lines) and a digital pixel driving method (full lines). In an analog driven pixel, the pixel luminance is constant during each image frame period and it can be different from frame to frame. The pixel luminance can have 2n different levels. In a digital driven pixel, a pixel is at full luminance(ON) during part of a frame period and at zero luminance (OFF) during the remaining part of the frame period. FIG. 4 is only a schematic representation, not showing a division in sub-frames for the digital driving approach.